KEAS =20×logGEA×RC× RDOWN

RUP+RDOWN =−KPSfC

(19)

where

– KEA is gain of the error amplifier network

– KPS is the gain of the power stage

– GEA is the transconductance of the amplifier, the typical value of GEA = 175µA / V

3. Set the compensation zero capacitor, CC .

• Place the compensation zero at the power stage pole position of ROUT, COUT to get:

fZ= 1

2π×RC×CC

(20)

• Set ƒZ = ƒP, and get:

CC=ROUT×COUT

2×RC

(21)

4. Set the compensation pole capacitor, CP .

• Place the compensation pole at the zero produced by the RESR and the COUT. Canceling unhelpful effects

of the ESR zero is useful.

fP2= 1

2π×RC×CP

(22)

fESR= 1

2π×RESR×COUT

(23)

• Set ƒP2 = ƒESR, and get:

CP=RESR×COUT

RC

(24)

• If the calculated value of CP is less than 10pF, the value can be neglected.

Designing the loop for greater than 45° of phase margin and greater than 6dB gain margin eliminates output

voltage ringing during the line and load transient. The RC = 61.9kΩ , CC = 680pF for this design example.

8.2.2.7 Selecting the Bootstrap Capacitor

The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side

FET device gate during the turn-on of each cycle and also supplies charge for the bootstrap capacitor. The

recommended value of the bootstrap capacitor is 20nF to 200nF. CBST must be a good quality, low-ESR ceramic

capacitor located at the pins of the device to minimize potentially damaging voltage transients caused by trace

inductance. A value of 100nF is selected for this design example.

TPS61371

SLVSI31 – APRIL 2026

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