IL

Load

VOUT

PFM

PWM

VOUT_PFM

VOUT_NORM

ICLAMP_LOW

TOFF longer with

lower current

TON = (L * I CLAMP_LOW) /

VIN

Figure 6-2. Auto PFM Operation Behavior

6.4.3 Forced PWM Mode

In forced PWM mode, the TPS61371 keeps the switching frequency constant across the whole load range.

When the load current decreases, the output of the internal error amplifier decreases as well to lower the

inductor peak current and delivers less power. The high-side FET is not turned off even if the current through the

FET goes negative to keep the switching frequency be the same as that of the heavy load.

6.4.4 Mode Selectable

There is a MODE pin to configure the TPS61371 into two different operation modes. The device works in forced

PWM mode when mode pin is high. When the MODE pin is pulled to low, the work mode depends on the FPWM

bit in the CONTROL register. See also the FPWM bit in Table 7-3 for detailed I2C settings.

6.5 Programming

6.5.1 Serial Interface Description

I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see NXP

Semiconductors, UM10204 – I2C-Bus Specification and User Manual). The bus consists of a data line (SDA)

and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high.

All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA, and SCL. A controller

device, typically a microcontroller or a digital signal processor, controls the bus. The controller is responsible for

generating the SCL signal and device addresses. The controller also generates specific conditions that indicate

the START and STOP of data transfer. A target device receives and transmits data on the bus under control of

the controller device.

The device works as a target and supports the following data transfer modes, as defined in the I2C-Bus

Specification:

• Standard-mode (100Kbps)

• Fast-mode (400Kbps)

• Fast-mode Plus (1Mbps)

The interface adds flexibility to the power supply design, enabling most functions to be programmed to new

values, depending on the instantaneous application requirements. Register contents remain intact as long as

supply voltage remains above VIT+(POR).

The data transfer protocol for standard and fast modes is exactly the same, therefore, the protocol is referred to

as F/S-mode in this document. The device supports 7-bit addressing; 10-bit addressing and general call address

are not supported. The device 7-bit address is programmable by ADDR pin.

To make sure that the I2C function in the device is correctly reset, TI recommends that the I2C controller initiates

a STOP condition on the I2C bus after the initial power up of SDA and SCL pullup voltages.

www.ti.com

TPS61371

SLVSI31 – APRIL 2026

Copyright © 2026 Texas Instruments Incorporated

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