TPS61371 datasheet(3/38 Pages) TI2

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4 Pin Configuration and Functions

VOUT

VIN

SDA

COMP

MODE

TPS61371

BST

SCL

ADDR

GND

Figure 4-1. VAR Package, 14-Pin WQFN-HR (Top View)

Table 4-1. Pin Functions

TYPE(1)

DESCRIPTION

NUMBER

NAME

1, 2

VOUT

PWR

Boost converter output

3, 14

PWR

The switching node pin of the converter. This pin is connected to the drain of the internal

low-side FET and the source of the internal high-side FET. The pin-3 and pin-14 SW must

be connected together. And put the inductor close to the pin-3 SW

VIN

IC power supply input

BST

Power supply for the high-side FET gate driver. A capacitor must be connected between

this pin and the SW pin.

Enable logic input. Logic low level disables the device output. Logic high level and

CONVERTER_EN = 1 enable the device output.

MODE

Operation mode selection pin.

MODE = high, the device is in forced PWM mode and keeps the switching frequency

constant across the whole load range, regardless of what the FPWM bit is set to MODE

= low, the device work mode depends on the FPWM bit (bit = 0: auto PFM mode; bit = 1:

FPWM mode).

ADDR

I2C target address set pin. See also Table 6-2.

SDA

I/O

I2C serial interface data. Pull this pin up to the I2C bus voltage with a resistor.

SCL

I2C serial interface clock. Pull this pin up to the I2C bus voltage with a resistor.

COMP

Output of the internal error amplifier. The loop compensation network must be connected

between this pin and GND.

Output voltage feedback. A resistor divider connecting to this pin sets the default output

voltage.

GND

—

Ground

(1)

PWR = power, I = input, O = output

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TPS61371

SLVSI31 – APRIL 2026

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