FN6690 datasheet(13/19 Pages) RENESAS

13 / 19 page

ISL12008 I2C Real Time Clock with Battery Backup

FN6690 Rev 1.00

Page 13 of 19

Sep 26, 2008

high. The FT/OUT pin voltage level is controlled by the voltage

of the pull-up resistor on FT/OUT pin. When the OUT is set to

“0” and FT is set to “0”, the FT/OUT pin is set to logic level low.

The voltage level of FT/OUT is set to VOL level. The OUT bit is

set to “1” on power-up. The FT/OUT pin is an open drain output

requires the use of a pull-up resistor.

Alarm Registers

Addresses [0Ch to 11h]

The Alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make the

comparison. Note that there is no alarm byte for year and sub-

second, and the register order for Alarm register is not a 100%

matching to the RTC register so please take caution on

programming the alarm function.

The alarm function works as a comparison between the alarm

registers and the RTC registers. As the RTC advances, the

alarm will be triggered once a match occurs between the alarm

registers and the RTC registers. Any one alarm register,

multiple registers, or all registers can be enabled for a match.

To clear an alarm, the ALM status bit must be set to “0” with a

write. Note that if the ARST bit is set to “1” (address 0Bh, bit 7),

the ALM bit will automatically be cleared when the status

I2C Serial Interface

The ISL12008 supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the bus

as a transmitter and the receiving device as the receiver. The

device controlling the transfer is the master and the device

being controlled is the slave. The master always initiates data

transfers and provides the clock for both transmit and receive

operations. Therefore, the ISL12008 operates as a slave

device in all applications.

All communication over the I2C bus is conducted by sending

the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (see Figure 10). On

power-up of the ISL12008, the SDA pin is in the input mode.

All I2C bus operations must begin with a START condition,

which is a HIGH to LOW transition of SDA while SCL is HIGH.

The ISL12008 continuously monitors the SDA and SCL lines

for the START condition and does not respond to any

command until this condition is met (see Figure 10). A START

condition is ignored during the power-up sequence.

All I2C bus operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL

is HIGH (see Figure 10). A STOP condition at the end of a read

operation or at the end of a write operation to memory only

places the device in its standby mode.

An acknowledge (ACK) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after transmitting

8 bits. During the ninth clock cycle, the receiver pulls the SDA

line LOW to acknowledge the reception of the 8 bits of data

(see Figure 11).

The ISL12008 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL12008 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

FIGURE 10. VALID DATA CHANGES, START, AND STOP CONDITIONS

SDA

SCL

START

DATA

STOP

STABLE

CHANGE

DATA

STABLE

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