FN6690 datasheet(15/19 Pages) RENESAS

15 / 19 page

ISL12008 I2C Real Time Clock with Battery Backup

FN6690 Rev 1.00

Page 15 of 19

Sep 26, 2008

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The 7 MSBs are the device identifiers. These

bits are “1101000”.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W bit is a “1”, then a

read operation is selected (refer to Figure 16). When this R/W

bit is a “0” , then a write operation (refer to Figure 12).

After loading the entire Slave Address Byte from the SDA bus,

the ISL12008 compares the Slave bit and device select bits

with “1101000”. Upon a correct compare, the device outputs an

acknowledge on the SDA line.

Following the Slave Byte is a one byte word address. The word

address is either supplied by the master device or obtained

from an internal counter. On power-up, the internal address

counter is set to address 0h, so a current address read of the

CCR array starts at address 0h. When required, as part of a

random read, the master must supply the 1 Word Address

Bytes, as shown in Figure 14.

In a random read operation, the slave byte in the “dummy

write” portion must match the slave byte in the “read” section.

For a random read of the Clock/Control Registers, the slave

byte must be “1101000x” in both places.

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte, and

a STOP condition. After each of the three bytes, the ISL12008

responds with an ACK. After received the STOP condition, the

ISL12008 writes the data into the memory, then the I2C bus

enters a standby state. After a Write operation, the internal

address pointer will remain at the address for the last data byte

written.

Read Operation

A Read operation consists of a three byte instruction followed

by one or more Data Bytes (see Figure 14). The master

initiates the operation issuing the following sequence: a

START, the Identification byte with the R/W bit set to “0”, an

Address Byte, a second START, and a second Identification

byte with the R/W bit set to “1”. After each of the three bytes,

the ISL12008 responds with an ACK. Then the ISL12008

transmits Data Bytes as long as the master responds with an

ACK during the SCL cycle following the eighth bit of each byte.

The master terminates the read operation (issuing a STOP

condition) following the last bit of the last Data Byte (see Figure

14).

The Data Bytes are from the memory location indicated by an

internal address pointer. This internal address pointer initial

value is determined by the Address Byte in the Read operation

instruction, and increments by one during transmission of each

Data Byte.

FIGURE 13. SLAVE ADDRESS, WORD ADDRESS, AND DATA

BYTES

SLAVE

ADDRESS BYTE

DATA BYTE

R/W

WORD ADDRESS

FIGURE 14. READ SEQUENCE

SIGNALS

FROM THE

MASTER

SIGNALS FROM

THE SLAVE

SIGNAL AT

SDA

IDENTIFICATION

BYTE WITH

R/W = 0

ADDRESS

BYTE

IDENTIFICATION

BYTE WITH

R/W = 1

LAST READ

DATA BYTE

FIRST READ

DATA BYTE

1000

10 00

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