ADS7229IPWR datasheet(32/46 Pages) TI

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TAG Mode

Chain Mode

ADS7229

ADS7230

SBAS437 – MAY 2008........................................................................................................................................................................................................ www.ti.com

The falling edge of FS/CS should not be placed at the precise moment of the end of a conversion; otherwise, the

data may be corrupt. There must be a minimum of at least one conversion clock (CCLK) delay at the end of a

conversion. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is

placed after the end of a conversion, the current conversion result is read.

The conversion result is 12-bit data in straight binary format as shown in Table 5. Generally, 12 SCLKs are

necessary, but there are exceptions where more than 12 SCLKS are required (see Table 6). Data output from

the serial output (SDO) is left-adjusted, MSB first. The 12-bit conversion result is followed by '0000', the TAG bit

(if enabled), and additional zeros. SDO remains low until FS/CS is brought high again.

Table 5. Ideal Input Voltages and Output Codes

DIGITAL OUTPUT

DESCRIPTION

ANALOG VALUE

STRAIGHT BINARY

Full-scale range

VREF

BINARY CODE

HEX CODE

Least significant bit (LSB)

VREF/4096

Full-scale

+VREF – 1LSB

1111 1111 1111

FFF

Midscale

VREF/2

1000 0000 0000

800

Midscale – 1LSB

VREF/2– 1LSB

0111 1111 1111

7FF

Zero

0000 0000 0000

000

SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.

NOTE:

Whenever SDO is not in 3-state mode (that is, when FS/CS is low), a portion of the

conversion result is output at the SDO pin. The number of bits depends on how many

SCLKs are supplied. For example, a manual select channel command cycle requires

4 SCLKs; therefore, 4MSBs of the conversion result are output at SDO. The exception

is that SDO outputs all 1s during the cycle immediately after any reset (POR or

software reset).

If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all

12 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is better

to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in Auto nap mode).

The ADS7230 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the

converted result. An address bit is added after the LSB read out from SDO that indicates which channel the

result came from if TAG mode is enabled. This address bit is '0' for channel 0 and '1' for channel 1. The

converter requires more than the 16 SCLKs that are required for a 4-bit command plus 12-bit CFR or 12 data bits

followed by '0000' because of the additional TAG bit.

The ADS7229/30 can operate as a single converter or in a system with multiple converters. System designers

can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading the devices in a

daisy-chain when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as

a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This

configuration is chain mode operation. A typical connection of three converters is shown in Figure 61.

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ADS7229IPWR Datasheet(PDF) 32 Page - Texas Instruments

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