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ADS7229IPWR Datasheet(PDF) 25 Page - Texas Instruments |
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ADS7229IPWR Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 46 page ![]() Auto Channel Select Mode Start of a Conversion Status Output EOC/INT ADS7229 ADS7230 www.ti.com........................................................................................................................................................................................................ SBAS437 – MAY 2008 Channel selection can also be done automatically if auto channel select mode is enabled. This mode is the default channel select mode. The dual channel converter, ADS7230, has an onboard 2-to-1 MUX. If the device is programmed for auto channel select mode, then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to '1' for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to '0'. The end of sampling instance (EOS) or acquisition is the same as the start of a conversion. This event is initiated by bringing the CONVST pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that require a simultaneous sample/hold with multiple converters. The ADS7229/30 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS7229/30 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 857ns with a 21MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as an auto trigger, the next conversion automatically starts three conversion clocks (CCLK) after the end of a conversion. These three conversion clocks are used as the acquisition time. In this case, the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes. Table 1. Different Types of Conversion MODE SELECT CHANNEL START CONVERSION Auto Channel Select(1) Auto Trigger Automatic No need to write channel number to the CMR. Use internal sequencer for the Start a conversion based on the conversion ADS7230. clock CCLK. Manual Channel Select Manual Trigger Manual Write the channel number to the CMR. Start a conversion with CONVST. (1) Auto channel select should be used with the TAG bit enabled. When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes low immediately after CONVST goes low when the manual trigger is programmed. EOC stays low throughout the conversion process and returns high when the conversion ends. The EOC output goes low for three conversion clocks after the previous rising edge of EOC, if auto trigger is programmed. This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can also be used as INT (CFR_D[7:6] = 1, 0), which is set low as the end of a conversion is brought high (cleared) by the next read cycle. The polarity of this pin, used as either function (EOC or INT), is programmable through CFR_D7. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link(s): ADS7229 ADS7230 |
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