Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ADS7229IPWR Datasheet(PDF) 8 Page - Texas Instruments

Click here to check the latest version.
Part # ADS7229IPWR
Description  LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
PDF  46 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS7229IPWR Datasheet(HTML) 8 Page - Texas Instruments

Back Button ADS7229IPWR Datasheet HTML 4Page - Texas Instruments ADS7229IPWR Datasheet HTML 5Page - Texas Instruments ADS7229IPWR Datasheet HTML 6Page - Texas Instruments ADS7229IPWR Datasheet HTML 7Page - Texas Instruments ADS7229IPWR Datasheet HTML 8Page - Texas Instruments ADS7229IPWR Datasheet HTML 9Page - Texas Instruments ADS7229IPWR Datasheet HTML 10Page - Texas Instruments ADS7229IPWR Datasheet HTML 11Page - Texas Instruments ADS7229IPWR Datasheet HTML 12Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 46 page
background image
TIMING CHARACTERISTICS
(1) (2) : 1.8V
ADS7229
ADS7230
SBAS437 – MAY 2008........................................................................................................................................................................................................ www.ti.com
All specifications typical at –40
°C to 85°C, +VA = 2.7 V, and +VBD = 1.8V, unless otherwise noted.
ADS7229, ADS7230
PARAMETER
MIN
TYP
MAX
UNIT
External, 3V
≤ +VA ≤ 3.6V,
0.5
21
fCCLK = 1/2 fSCLK
External, 2.7V
≤ +VA ≤ 3V,
fCCLK
Frequency, conversion clock, CCLK
0.5
18.9
MHz
fCCLK = 1/2 fSCLK
Internal,
20
22.3
23.5
fCCLK = 1/2 fSCLK
t1
Setup time, falling edge of CS to EOC
1
CCLK
t2
Hold time, falling edge of CS to EOC
0
ns
tCL
Pulse duration, CONVST low
40
ns
t3
Hold time, falling edge of CS to EOS
20
ns
t4
Setup time, rising edge of CS to EOS
20
ns
t5
Hold time, rising edge of CS to EOS
20
ns
Setup time, falling edge of CS to first t6 falling
t6
5
ns
SCLK
tSCLKL
Pulse duration, SCLK low
8
tSCLK – 8
ns
tSCLKH
Pulse duration, SCLK high
8
tSCLK – 8
ns
All modes,
23.8
2000
3V
≤ +VA ≤ 3.6V
tSCLK
Cycle time, SCLK
ns
All modes,
26.5
2000
2.7V
≤ +VA < 3V
tH2
Hold time, falling edge of SCLK to SDO invalid 10pF Load
7.5
ns
tD1
Delay time, falling edge of SCLK to SDO valid
10pF Load
16
ns
10pF Load,
13
2.7V
≤ +VA ≤ 3V
Delay time, falling edge of CS to SDO valid,
tD2
ns
SDO MSB output
10pF Load,
11
3V
≤ +VA ≤ 3.6V
tS1
Setup time, SDI to falling edge of SCLK
8
ns
tH1
Hold time, SDI to falling edge of SCLK
4
ns
Delay time, rising edge of CS/FS to SDO
tD3
8
ns
3-state
Setup time, 16th falling edge of SCLK t7
t7
10
ns
before rising edge of CS/FS
(1)
All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
(2)
See timing diagrams.
8
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7229 ADS7230



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com