4282 datasheet(4/69 Pages) RENESAS

4 / 69 page

Rev.1.33

Mar 18, 2004

page 4 of 67

4282 Group

CONNECTIONS OF UNUSED PINS

D0–D7

E0, E1

G0–G3

Connection

Open or connect to VDD pin (Note 1).

Set the output latch to “1” and open, or

connect to VDD pin (Note 2).

Open or connect to VSS pin.

Set the output latch to “1” and open, or

connect to VDD pin (Note 2).

Notes 1: Ports D4–D7: Set the bit 2 (PU02) of the pull-down control register PU1 to “0” by software and turn the pull-down transistor

OFF.

2: Set the corresponding bits of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF.

(Note in order to set the output latch to “1” to make pins open)

• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “1” by software.

Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.

• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away

(caused by noise).

(Note when connecting to VSS and VDD)

• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.

PORT FUNCTION

Control

bits

1 bit

Output:

2 bits

Input:

3 bits

4 bits

1 bit

Control

instructions

CLD

SZD

OEA

IAE

OGA

IAG

SCAR

RCAR

Control

registers

PU1

PU0

Output structure

P-channel open-drain

CMOS

Input/

Output

(4)

I/O

(4)

I/O

(2)

Input

(1)

I/O

(4)

Output

(1)

Remark

Pull-down function and

key-on wakeup function

(programmable)

Pull-down function and

key-on wakeup function

(programmable)

Pull-down function and

key-on wakeup function

(programmable)

D0–D3

D4–D7

G0–G3

CARR

Port

Port D

Port E

Port G

Port CARR

DEFINITION OF CLOCK AND CYCLE

• System clock (STCK)

The system clock is the source clock for controlling this product.

It can be selected as shown below whether to use the CCK

instruction.

CCK instruction

When not using

When using

Instruction clock

f(XIN)/32

f(XIN)/4

System clock

f(XIN)/8

f(XIN)

• Instruction clock (INSTCK)

The instruction clock is a signal derived by dividing the system

clock by 4, and is the basic clock for controlling CPU. The one

instruction clock cycle is equivalent to one machine cycle.

• Machine cycle

The machine cycle is the cycle required to execute the

instruction.

4282 Datasheet(PDF) 4 Page - Renesas Technology Corp

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