4282 datasheet(63/69 Pages) RENESAS

63 / 69 page

Rev.1.33

Mar 18, 2004

page 63 of 67

4282 Group

Fig. 33 Timing at program verifying

and pull the PGM pin to “L.” When this is done, the program

data is programmed to the specified address.

(4) Program

Input command code 2516 in the first transfer. Proceed and

input the low-order 8 bits and high-order 8 bits of the address

and the low-order 8 bits and high-order 8 bits of program data,

Fig. 32 Timing at programming

(5) Program verify

Input command code 3516 in the first transfer. Proceed and

input the low-order 8 bits and high-order 8 bits of the address

and the low-order 8 bits and high-order 8 bits of program data,

and pull the PGM pin to “L.” When this is done, the program

data is programmed to the specified address. Then, when the

PGM pin is pulled to “L” again after it is released back to “H,”

the address programmed with the program command is read

and verified and stored into the internal data latch. When the

PGM pin is released back to “H” and serial clock is input to the

SCLK pin, the verify data that has been stored into the data

latch is serially output from the SDA pin.

Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is

placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit).

10 1 0010 0

Commanf code input (2516)Program address input (L) Program address input (H)

SCLK

SDA

PGM

Program

tCH

Program data input (L)

tCP

tWP

tCH

Program data input (H)

tCH

00 000 0 0

tCH

A8 A9

0000 0

A10

1 0 1 01 100

Command code input (3516)

Program address input (L)

Program address input (H)

SCLK

SDA

PGM

tCH

Program data input (L)

tCP

tWP

tCH

Program data input (H)

tCH

00 0000 0

tCH

A8 A9

0000 0

Program

tCR

tRC

SCLK

SDA

PGM

Verify

tWR

Verify data output (L)

Verify data output (H)

tCH

0000 000

A10

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