3850 datasheet(46/101 Pages) RENESAS

46 / 101 page

Rev.3.01

2003.06.20

page 46 of 98

3850 Group (Spec.H)

Fig. 50 Internal status at reset (spec. H)

Note : X : Not fixed

Since the initial values for other than above mentioned registers and

RAM contents are indefinite at reset, they must be set.

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

(33)

Address Register contents

0016

FF16

0116

0016

FF16

0016

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Port P4 (P4)

Port P4 direction register (P4D)

Serial I/O2 control register 1 (SIO2CON1)

Serial I/O2 control register 2 (SIO2CON2)

Serial I/O2 register (SIO2)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIOSTS)

Serial I/O1 control register (SIOCON)

UART control register (UARTCON)

Baud rate generator (BRG)

PWM control register (PWMCON)

PWM prescaler (PREPWM)

PWM register (PWM)

Prescaler 12 (PRE12)

Timer 1 (T1)

Timer 2 (T2)

Timer XY mode register (TM)

Prescaler X (PREX)

Timer X (TX)

Prescaler Y (PREY)

Timer Y (TY)

Timer count source selection register (TCSS)

A-D control register (ADCON)

A-D conversion low-order register (ADL)

A-D conversion high-order register (ADH)

0 0 00 01 11

1 0 00 00 00

XX XXX XXX

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

003416

003516

003616

1 1 10 00 00

XX XXX XXX

000 1 0 0 0 0

XX XXX XXX

0016

(34)

(35)

(36)

(37)

(38)

(39)

(40)

(41)

(42)

(43)

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

(PS)

(PCH)

(PCL)

Address

XXXXX 1 XX

FFFD16 contents

FFFC16 contents

00 1 1 11 1 1

01 0 0 10 0 0

MISRG

Watchdog timer control register (WDTCON)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Interrupt control register 2 (ICON2)

Processor status register

Program counter

000 0 0 0

3850 Datasheet(PDF) 46 Page - Renesas Technology Corp

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