3850 datasheet(33/101 Pages) RENESAS

33 / 101 page

Rev.3.01

2003.06.20

page 33 of 97

3850 Group (Spec.H/A)

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O1 mode selection bit (b6) of the serial I/O1

control register to “0”.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer register, and receive data is read

from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 28 Block diagram of UART serial I/O1

XIN

1/4

PE FE

1/16

Data bus

Receive buffer register

Address 001816

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C16

ST/SP/PA generator

Transmit buffer register

Data bus

Transmit shift register

Address 001816

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Address 001916

ST detector

SP detector

UART control register

Address 001B16

Character length selection bit

Address 001A16

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O1 synchronous clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O1 control register

P26/SCLK1

Serial I/O1 status register

P24/RXD

P25/TXD

3850 Datasheet(PDF) 33 Page - Renesas Technology Corp

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