3850 datasheet(15/101 Pages) RENESAS

15 / 101 page

Rev.3.01

2003.06.20

page 15 of 98

3850 Group (Spec.H)

Fig. 11 Memory map of special function register (SFR) (spec. H)

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Port P4 (P4)

Port P4 direction register (P4D)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIOSTS)

Serial I/O1 control register (SIOCON)

UART control register (UARTCON)

Baud rate generator (BRG)

Interrupt control register 2 (ICON2)

A-D conversion low-order register (ADL)

Prescaler Y (PREY)

Timer Y (TY)

A-D control register (ADCON)

A-D conversion high-order register (ADH)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Prescaler 12 (PRE12)

Timer 2 (T2)

Prescaler X (PREX)

Timer X (TX)

Timer 1 (T1)

Timer XY mode register (TM)

Reserved ✽

MISRG

Watchdog timer control register (WDTCON)

PWM control register (PWMCON)

PWM prescaler (PREPWM)

PWM register (PWM)

Timer count source selection register (TCSS)

Serial I/O2 control register 1 (SIO2CON1)

Serial I/O2 control register 2 (SIO2CON2)

Serial I/O2 register (SIO2)

✽ Reserved : Do not write any data to this addresses, because these areas are reserved.

Reserved ✽

0FFE16

Flash memory control register (FMCR)

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