3850 datasheet(91/101 Pages) RENESAS

91 / 101 page

Rev.3.01

2003.06.20

page 91 of 98

3850 Group (Spec.H)

Timing requirements

Table 34 Timing requirements (1) (spec. H)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Limits

XIN cycle

Parameter

Min.

125

200

800

370

220

100

1000

400

200

Typ.

Max.

Symbol

Unit

Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input setup time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 clock input setup time

Serial I/O2 clock input hold time

Table 35 Timing requirements (2) (spec. H)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

tWH(INT)

tWL(INT)

tC(SCLK1)

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD-SCLK1)

th(SCLK1-RxD)

tC(SCLK2)

tWH(SCLK2)

tWL(SCLK2)

tsu(SIN2-SCLK2)

th(SCLK2-SIN2)