M37160MF datasheet(41/131 Pages) RENESAS

41 / 131 page

Rev.1.01

2003.11.13

page 41 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

Fig. 8.6.13 Address Data Communication Format

SSlave address

DataA

DataA/A

R/W

7 bits

“0”

1 to 8 bits

SSlave address

Data

AData

7 bits

“1”

1 to 8 bits

(1) A master-transmitter transmits data to a slave-receiver

Slave address

1st 7 bits

Data

7 bits

“0”

8 bits

1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

Slave address

2nd byte

DataA/A

1 to 8 bits

Slave address

1st 7 bits

7 bits

“0”

8 bits

7 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

Slave address

2nd byte

Data

1 to 8 bits

Slave address

1st 7 bits

Data

1 to 8 bits

“1”

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

S: START conditionP : STOP condition

A: ACK bitR/W : Read/Write bit

Sr: Restart condition

From master to slave

From slave to master

R/W

8.6.12 Precautions when using multi-master

I2C-BUS interface

(1) Read-modify-write instruction

Precautions for executing the read-modify-write instructions such as

SEB and CLB, is executed for each register of the multi-master I2C-

BUS interface are described below.

•I2C data shift register (S0)

When executing the read-modify-write instruction for this register

during transfer, data may become an arbitrary value.

•I2C address register (S0D)

When the read-modify-write instruction is executed for this register

at detection of the STOP condition, data may become an arbitrary

______

value because hardware changes the read/write bit (RBW) at the

above timing.

•I2C status register (S1)

Do not execute the read-modify-write instruction for this register

because all bits of this register are changed by hardware.

•I2C control register (S1D)

When the read-modify-write instruction is executed for this register

at detection of the START condition of the byte transfer, data may

become an arbitrary value because hardware changes the bit

counter (BC0–BC2) at the above timing.

•I2C clock control register (S2)

The read-modify-write instruction can be executed for this register.

(2) START condition generation procedure us-

ing multi-master

➀ Procedure example (The necessary conditions for the procedure

are described in ➁ to ➄ below).

•

LDA

—

(Take out of slave address value)

SEI

(Interrupt disabled)

BBS 5,S1,BUSBUSY

(BB flag confirmation and branch process)

BUSFREE:

STA S0

(Write slave address value)

LDM #$F0, S1

(Trigger START condition generation)

CLI

(Interrupt enabled)

•

BUSBUSY:

CLI

(Interrupt enabled)

•

➁ Use “STA,” “STX” or “STY” of the zero page addressing instruc-

tion for writing the slave address value to the I2C data shift register.

➂ Use “LDM” instruction for setting trigger of START condition gen-

eration.

➃ Write the slave address value of ➁ and set trigger of START con-

dition generation as in ➂ continuously, as shown in the procedure

example.

➄ Disable interrupts during the following three process steps:

• BB flag confirmation

• Write slave address value

• Trigger of START condition generation

When the condition of the BB flag is bus busy, enable interrupts

immediately.

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