M37160MF datasheet(12/131 Pages) RENESAS

12 / 131 page

Rev.1.01

2003.11.13

page 12 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

8. FUNCTION BLOCK DESCRIPTION

8.1 CENTRAL PROCESSING UNIT (CPU)

This microcomputer uses the standard 740 Family instruction set.

Refer to the table of 740 Family addressing modes and machine

instructions or the SERIES 740 <Software> User’s Manual for de-

tails on the instruction set.

Availability of 740 Family instructions are as follows:

The FST, SLW instruction cannot be used.

The MUL, DIV, WIT and STP instructions can be used.

8.1.1 CPU Mode Register

The CPU mode register includes a stack page selection bit and inter-

nal system clock selection bit. The CPU mode register is allocated at

address 00FB16.

Fig. 8.1.1 CPU Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

After reset RW

CPU Mode Register

0, 1

3, 4

Name

Functions

Processor mode bits

(CM0, CM1)

0 0: Single-chip mode

0 1:

1 0:

Not available

1 1:

Fix these bits to “1.”

Stack page selection

bit (CM2) (See note1)

b1 b0

0: 0 page

1: 1 page

Main Clock (XIN) stop bit

(CM6)

CPU mode register (CM) [Address 00FB16]

R W

XCOUT drivability

selection bit (CM5)

0: LOW drive

1: HIGH drive

0: Oscillating

1: Stopped

Internal system clock

selection bit

(CM7) (See note2)

0: XIN selected

(high-speed mode)

1: XCIN–XCOUT selected

or FSCIN input selected

(low-speed mode)

Note 1: This bit is set to “1” after the reset release.

2: XCIN-XCOUT and FSCIN are switched over using Clock

Control Register 2 (address 021116) bit 2.

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