M37160MF datasheet(62/131 Pages) RENESAS

62 / 131 page

Rev.1.01

2003.11.13

page 62 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

Fig. 8.10.14 Relation between Field Determination Flag and Display Font

Field

Even

Odd

Field

determination

flag(Note)

Display dot line

selection bit

Display dot line

0 (T2 > T1)

1 (T3 < T2)

When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208

Both HSYNC cignal and VSYNC signal are negative-polarity input

) to “0.”

OSD ROM font configuration diagram

Dot line 0

Dot line 1

Odd

Dot line 0

Dot line 1

(n – 1) field

(Odd-numbered)

0.25 to 0.50[

µs] at

f(XIN) = 8 MHz

OSD1 mode

OSD2,CD OSD mode

HSYNC

VSYNC and

VSYNC

control

signal

in microcom-

puter

Upper :

VSYNC signal

Lower :

VSYNC control

signal in

micro-

computer

(n) field

(Even-numbered)

(n + 1) field

(Odd-numbered)

When the display dot line selection bit is “0,”

the “

” font is displayed at even field, the

“

” font is displayed at odd field. Bit 6 of the

I/O polarity control register can be read as the

field determination flag : “1” is read at odd field,

“0” is read at even field.

Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in

the microcomputer.

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