M37160MF datasheet(86/131 Pages) RENESAS

86 / 131 page

Rev.1.01

2003.11.13

page 86 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

Fig.8.13.3 Clock frequency setting register

Fig.8.13.5 Ckock control register 2

Fig.8.13.4 Ckock control register 1

Clock frequency set register(CFS) [Address 021016]

Clock frequency set register

0 to

b7 b6 b5 b4 b3 b2 b1 b0

Clock frequency bit

(CFS 0 to 7)

0000101

FSCIN=4.43MHz

8.86

26.58

Main clock frequency

f(XIN)

[MHz]

Reference clock input Setting value

Set to 0B16

OSD clock frequency

f(OSC)

[MHz]

Name

Functions

After reset R W

R W

Note: Do not set other than the values shown above to CFS.

Clock control register 1

Clock control register 1 (CC1) [Address 00CD16]

b7 b6 b5 b4 b3 b2 b1 b0

000

System clock generating

circuit control bit (CC10)

0:Operation

1: Stop

Fix these bits to "0"

1 to

Name

Functions

After reset R W

R W

4 to

b7 b6 b5 b4 b3 b2 b1 b0

0: FSCIN input signal

1: XCIN-XcoUT

000

Note: This bit is valid when the CPU Mode Register (address 00FB16)

bit 7 (CM7) is set to 1.

Fix these bits to "0"

Fix this bit to "1"

Clock control register 2 (CC2) [Address 021116]

Name

Functions

After reset R W

0,1

Clock sauce switch bit (Note)

(CC22)

Clock control register 2

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