M37160MF datasheet(90/131 Pages) RENESAS

90 / 131 page

Rev.1.01

2003.11.13

page 90 of 130

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP

Fig.8.13.9 State Transitions of System Clock(2)

CM7=1

CM7=0

CM6=0

CC10=0

CM6=1

CC10=1

2. When using the 32 kHz oscillating

Clock Control Register 2 (address 021116) bit 2 = "1"

The above example assumes that the FSCIN and XCIN pins have 4.43 MHz and 32 kHz signals applied, respectively.

The

φ indicates the internal clock.

CPU mode register

(Address 00FB16)

0: oscillating

1: stopped

CM6: Main clock f(XIN) stop bit

FSCIN=4.43MHz

f(XIN)=8.86MHz

φ is stopped (“H”)

Timer operating

32kHz oscillating

f(XIN)=8.86MHz

φ)=f(XIN)/2

FSCIN=4.43MHz

32kHz oscillating

FSCIN=stopped

φ is stopped (“H”)

f(XIN)=stopped

32kHz stopped

f(XIN)=stopped

φ is stopped (“H”)

Timer operating

FSCIN=4.43MHz

32kHz oscillating

f(XIN)=stopped

φ)=16MHz

FSCIN=4.43MHz

32kHz oscillating

f(XIN)=stopped

φ is stopped (“H”)

FSCIN=stopped

32kHz stopped

FSCIN=4.43MHz

f(XIN)=8.86MHz

φ)=16MHz

32kHz oscillating

Reset

WIT instruction

Interrupt

STP instruction

External INT

High-speed operation start

mode

CM7: Internal system clock selection bit

0: f(XIN) selected (high-speed mode)

1: XCIN-XCOUT selected or FSCIN input

(low-speed mode)

WIT instruction

Interrupt

STP instruction

External INT,

timer INT,

or SI/O INT

External INT

The program must

allow time for 8.86 MHz

oscillation to stabilize

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