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M37160MF Datasheet(PDF) 57 Page - Renesas Technology Corp |
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M37160MF Datasheet(HTML) 57 Page - Renesas Technology Corp |
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57 / 131 page  Rev.1.01 2003.11.13 page 57 of 130 M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP The vertical display start position is determined by counting the hori- zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), the count starts at the rising edge (falling edge) of HSYNC signal after the fixed cycle of the rising edge (falling edge) of VSYNC signal. So the interval from the rising edge (falling edge) of VSYNC signal to the rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) to avoid jitter. The polarity of HSYNC and VSYNC signals can select with the I/O po- larity control register (address 00D816). Fig. 8.10.7 Supplement Explanation for Display Position When bits 0 and 1 of the I/O polarity control register (address 00D816) are set to “1” (negative polarity) VSYNC signal input VSYNC control signal in microcomputer 0.25 to 0.50 [ µs] ( at f(XIN) = 8MHz) Period of counting HSYNC signal (See note 2) HSYNC signal input Not count 12345 Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more. 8 machine cycles or more 8 machine cycles or more |
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