SH7261 datasheet(846/1348 Pages) RENESAS

846 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 814 of 1312

REJ09B0320-0200

19.2.4

Memory Map

The diagram of the memory map is shown below.

H'000

H'002

H'004

H'006

H'008

H'00A

H'00C

H'020

H'022

H'02A

H'032

H'03A

H'042

H'04A

H'052

H'05A

H'0A0

H'0A4

H'100

H'104

H'108

H'10A

H'10C

H'10E

H'110

H'120

H'140

H'160

H'2E0

Bit 15

Bit 0

Bit 15

Bit 0

Master Control Register (MCR)

General Status Register(GSR)

Bit timing Configuration Register 1 (BCR1)

Bit timing Configuration Register 0 (BCR0)

Interrupt Request Register (IRR)

Interrupt Mask Register (IMR)

Mailbox-0 Control 1 (NMC, MBC, DLC)

Mailbox-1 Control/LAFM/Data etc.

Mailbox 0 Data (8 bytes)

Mailbox-2 Control/LAFM/Data etc.

Mailbox-3 Control/LAFM/Data etc.

Mailbox-15 Control/LAFM/Data etc.

Transmit Pending Register (TXPR1)

Transmit Pending Register (TXPR0)

Transmit Cancel Register (TXCR0)

Transmit Acknowledge Register (TXACK0)

Abort Acknowledge Register (ABACK0)

Data Frame Receive Pending Register (RXPR0)

Remote Frame Pending Register (RFPR0)

Mailbox Interrupt Mask Register (MBIMR0)

Unread Message Status Register (UMSR0)

Transmit Error Counter

(TEC)

Receive Error Counter

(REC)

Mailbox-0 Control 0

(STDID, EXTID, RTR, IDE)

LAFM

Note: The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed.

Addresses shown above are offset addrsses. As for actual addresses, see section 30, List of Registers.

Figure 19.2 RCAN-ET Memory Map

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