SH7261 datasheet(945/1348 Pages) RENESAS

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Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 913 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

General Broadcast Reception Acknowledgement

Set to 1 when the slave address is acknowledged as

H'FFF in broadcast reception. Like the receive

broadcast bit, this flag is valid when the slave/broadcast

reception is started. (This flag is changed at the time of

setting the RXS flag in IERSR.)

The previous value remains unchanged until the next

slave/broadcast reception is started. This flag is cleared

to 0 in slave normal reception.

0: (1) A unit is in slave reception

(2) When H'FFF is not acknowledged in the slave

address field in broadcast reception

1: When H'FFF is acknowledged in the slave address

field in broadcast reception

20.3.16

IEBus Transmit Status Register (IETSR)

IETSR detects events such as transmit start, transmit normal completion, and transmit error end.

Each status flag in IETSR corresponds to a bit in the IEBus transmit interrupt enable register

(IEIET) that enables or disables each interrupt. This register is cleared by writing 1 to each bit.

IETSR is initialized by a power-on reset or in deep standby.

76543210

Bit:

Initial value:

R/W:

00000000

R/(W)*

—

TXS

TXF

—

TXE

TTME

TXE

ACK

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

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