SH7261 datasheet(1071/1348 Pages) RENESAS

1071 / 1348 page

Section 23 D/A Converter (DAC)

Rev. 2.00 Sep. 07, 2007 Page 1039 of 1312

REJ09B0320-0200

23.3.1

D/A Data Registers 0 and 1 (DADR0 and DADR1)

DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be

performed. Whenever analog output is enabled, the values in DADR are converted and output to

the analog output pins.

DADR is initialized to H'00 by a power-on reset in deep standby mode or module standby mode.

7654321

00000000

R/W

Bit:

Initial value:

R/W:

23.3.2

D/A Control Register (DACR)

DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.

DACR is initialized to H'1F by a power-on reset in deep standby mode or module standby mode.

7654321

00011111

R/W

—————

Bit:

Initial value:

R/W:

DAOE1 DAOE0

DAE

—————

Bit

Bit Name

Initial

Value

R/W

Description

DAOE1

R/W

D/A Output Enable 1

Controls D/A conversion and analog output for channel 1.

0: Analog output of channel 1 (DA1) is disabled

1: D/A conversion of channel 1 is enabled. Analog output

of channel 1 (DA1) is enabled.

DAOE0

R/W

D/A Output Enable 0

Controls D/A conversion and analog output for channel 0.

0: Analog output of channel 0 (DA0) is disabled

1: D/A conversion of channel 0 is enabled. Analog output

of channel 0 (DA0) is enabled.

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