SH7672 datasheet(341/1292 Pages) RENESAS

341 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 315 of 1262

REJ09B0437-0100

8.3.8

DMA Operation Register (DMAOR)

The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the

priority level of channels at the DMA transfer. This register also shows the DMA transfer status.

0000000000000000

R/W

R/(W)* R/(W)* R/W

Note:

Only 0 can be written to clear the flag after 1 is read.

Bit:

Initial value:

R/W:



CMS[1:0]



PR[1:0]



NMIF

DME

Bit

Bit Name

Initial

Value

R/W

Description

15, 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

13, 12

CMS[1:0]

R/W

Cycle Steal Mode Select

These bits select either normal mode or intermittent

mode in cycle steal mode.

It is necessary that the bus modes of all channels be

set to cycle steal mode to make the intermittent mode

valid.

00: Normal mode

01: Setting prohibited

10: Intermittent mode 16

Executes one DMA transfer for every 16 cycles of

φ clock.

11: Intermittent mode 64

Executes one DMA transfer for every 64 cycles of

φ clock.

11, 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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