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SH7672 Datasheet(PDF) 345 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 345 Page - Renesas Technology Corp |
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345 / 1292 page ![]() Section 8 Direct Memory Access Controller (DMAC) Rev. 1.00 Nov. 14, 2007 Page 319 of 1262 REJ09B0437-0100 8.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3) The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and DMARS3 is for channels 6 and 7. Table 8.4 shows the specifiable combinations. This register can specify transfer requests from six SCIF sources, two IIC3 sources, two CMT sources, two USB sources, two SSI sources, and two SDHI sources. • DMARS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH1 MID[5:0] CH1 RID[1:0] CH0 RID[1:0] CH0 MID[5:0] • DMARS1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH3 MID[5:0] CH3 RID[1:0] CH2 RID[1:0] CH2 MID[5:0] • DMARS2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH5 MID[5:0] CH5 RID[1:0] CH4 RID[1:0] CH4 MID[5:0] • DMARS3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: CH7 MID[5:0] CH7 RID[1:0] CH6 RID[1:0] CH6 MID[5:0] Transfer requests from the various modules specify MID and RID as shown in table 8.4. |
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