SH7672 datasheet(342/1292 Pages) RENESAS

342 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 316 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

9, 8

PR[1:0]

R/W

Priority Mode

These bits select the priority level between channels

when there are transfer requests for multiple channels

simultaneously.

00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 >

CH5 > CH6 > CH7

01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 >

CH6 > CH3 > CH7

10: Setting prohibited

11: Round-robin mode (only supported in CH0 to CH3)

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/(W)* Address Error Flag

Indicates whether an address error has occurred by the

DMAC. When this bit is set, even if the DE bit in CHCR

and the DME bit in DMAOR are set to 1, DMA transfer

is not enabled. This bit can only be cleared by writing 0

after reading 1.

0: No DMAC address error

1: DMAC address error occurred

[Clearing condition]

• Writing 0 after reading AE = 1

NMIF

R/(W)* NMI Flag

Indicates that an NMI interrupt occurred. When this bit

is set, even if the DE bit in CHCR and the DME bit in

DMAOR are set to 1, DMA transfer is not enabled. This

bit can only be cleared by writing 0 after reading 1.

When the NMI is input, the DMA transfer in progress

can be done in one transfer unit. Even if the NMI

interrupt is input while the DMAC is not in operation,

the NMIF bit is set to 1.

0: No NMI interrupt

1: NMI interrupt occurred

[Clearing condition]

• Writing 0 after reading NMIF = 1

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