SH7672 datasheet(346/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 320 of 1262

REJ09B0437-0100

Table 8.4

DMARS Settings

Peripheral Module

Setting Value for One

Channel ({MID, RID})

MID

RID

Function

USB_0

H'03

B'000000

B'11



USB_1

H'07

B'000001

B'11



H'11

B'000100

B'01

Transmit

SDHI

H'12

B'000100

B'10

Receive

SSI_0

H'23

B'001000

B'11



SSI_1

H'27

B'001001

B'11



H'61

B'01

Transmit

IIC3_0

H'62

B'011000

B'10

Receive

H'81

B'10

Receive

SCIF_0

H'82

B'100000

B'01

Transmit

H'85

B'10

Receive

SCIF_1

H'86

B'100001

B'01

Transmit

H'89

B'10

Receive

SCIF_2

H'8A

B'100010

B'01

Transmit

CMT_0

H'FB

B'111110

B'11



CMT_1

H'FF

B'111111

B'11



When MID or RID other than the values listed in table 8.4 is set, the operation of this LSI is not

guaranteed. The transfer request from DMARS is valid only when the resource select bits

(RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set,

the transfer request source is not accepted.

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