SH7672 datasheet(348/1292 Pages) RENESAS

348 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 322 of 1262

REJ09B0437-0100

Start

Initial settings

(SAR, DAR, DMATCR, CHCR,

DMAOR, DMARS)

DE, DME = 1 and

NMIF, AE, TE = 0?

Yes

Transfer request

occurs?*1

Transfer (one transfer unit);

DMATCR – 1

→ DMATCR,

SAR and DAR updated

DMATCR = 0?

Yes

DEI interrupt request

(when IE = 1)

For a request from an

on-chip peripheral module,

the transfer acknowledge signal

is sent to the module.

When reload function is enabled,

RSAR

→ SAR, RDAR → DAR,

and RDMATCR

→ DMATCR

TE = 1

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

Transfer end

Transfer terminated

Normal end

Bus mode,

transfer request mode,

DREQ detection system

Yes

DMATCR=1/2 ?

HEI interrupt request

(when HE = 1)

HE=1

When the TC bit in CHCR is 0, or

for a request from an on-chip peripheral

module, the transfer acknowledge

signal is sent to the module.

Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the

DE and DME bits are set to 1.

2. DREQ level detection in burst mode (external request) or cycle steal mode.

3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode.

Upon detection

of the level of an external

request or at a request of an on-chip

peripheral module, is the

TEMASK bit set to 1?

Figure 8.2 DMA Transfer Flowchart

SH7672 Datasheet(PDF) 348 Page - Renesas Technology Corp

SH7672 Datasheet(HTML) 348 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL