SH7672 datasheet(352/1292 Pages) RENESAS

352 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 326 of 1262

REJ09B0437-0100

Table 8.8

Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits

CHCR

DMARS

RS[3:0] MID

RID

DMA Transfer

Request

Source

DMA Transfer

Request Signal

Transfer

Source

Transfer

Destination Bus Mode

USB_DMA0

(receive FIFO full)

D0FIFO

Any

000000 11

USB

USB_DMA0

(transmit FIFO empty)

Any

D0FIFO

USB_DMA1

(receive FIFO full)

D1FIFO

Any

000001 11

USB

USB_DMA1

(transmit FIFO empty)

Any

D1FIFO

Cycle steal

or burst

SDHI transmit

TXI (receive data empty)

Data register Any

000100

SDHI receive

RXI (transmit data full)

Any

Data

Cycle steal

DMA0 (transmit mode)

Any

SSITDR0

001000 11

SSI_0

DMA0 (receive mode)

SSIRDR0

Any

DMA1 (transmit mode)

Any

SSITDR1

001001 11

SSI_1

DMA1 (receive mode)

SSIRDR1

Any

Cycle steal

or burst

IIC3_0 transmit

TXI0 (transmit data empty)

Any

ICDRT0

011000

IIC3_0 receive

RXI0 (receive data full)

ICDRR0

Any

SCIF_0 transmit TXI0

(transmit FIFO data empty)

Any

SCFTDR_0

100000

SCIF_0 receive

RXI0

(receive FIFO data full)

SCFRDR_0

Any

SCIF_1 transmit TXI1

(transmit FIFO data empty)

Any

SCFTDR_1

100001

SCIF_1 receive

RXI1

(receive FIFO data full)

SCFRDR_1

Any

SCIF_2 transmit TXI2

(transmit FIFO data empty)

Any

SCFTDR_2

100010

SCIF_2 receive

RXI2

(receive FIFO data full)

SCFRDR_2

Any

Cycle steal

111110 11

CMT_0

CMI0 (compare match)

Any

1000

111111 11

CMT_1

CMI1 (compare match)

Any

Cycle steal

or burst

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