SH7672 datasheet(337/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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337 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 311 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

DMA Enable

Enables or disables the DMA transfer. In auto request

mode, DMA transfer starts by setting the DE bit and

DME bit in DMAOR to 1. In this case, all of the bits

TE, NMIF in DMAOR, and AE must be 0. In an

external request or peripheral module request, DMA

transfer starts if DMA transfer request is generated by

the devices or peripheral modules after setting the bits

DE and DME to 1. If the TEMASK bit is 1, the NMIF

and AE bits must be 0 upon detection of the low or

high level of an external request and at a request of

the peripheral module. If the TEMASK bit is 0, the TE

bit must also be 0. As with auto request mode, all of

the TE, NMIF, and AE bits must be 0 upon detection

of the rising or falling edge of an external request.

Clearing the DE bit to 0 can terminate the DMA

transfer.

0: DMA transfer disabled

1: DMA transfer enabled

Note:

Only 0 can be written to clear the flag after 1 is read.

SH7672 Datasheet(PDF) 337 Page - Renesas Technology Corp