SH7672 datasheet(333/1292 Pages) RENESAS

333 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 307 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Descriptions

15,14

DM[1:0]

R/W

Destination Address Mode

These bits select whether the DMA destination address

is incremented, decremented, or left fixed. (In single

address mode, DM1 and DM0 bits are ignored when

data is transferred to an external device with DACK.)

00: Fixed destination address

01: Destination address is incremented (+1 in 8-bit

transfer, +2 in 16-bit transfer, +4 in 32-bit transfer,

+16 in 16-byte transfer)

10: Destination address is decremented (–1 in 8-bit

transfer, –2 in 16-bit transfer, –4 in 32-bit transfer,

setting prohibited in 16-byte transfer)

11: Setting prohibited

13, 12

SM[1:0]

R/W

Source Address Mode

These bits select whether the DMA source address is

incremented, decremented, or left fixed. (In single

address mode, SM1 and SM0 bits are ignored when

data is transferred from an external device with DACK.)

00: Fixed source address

01: Source address is incremented (+1 in byte-unit

transfer, +2 in word-unit transfer, +4 in longword-

unit transfer, +16 in 16-byte-unit transfer)

10: Source address is decremented (–1 in byte-unit

transfer, –2 in word-unit transfer, –4 in longword-

unit transfer, setting prohibited in 16-byte-unit

transfer)

11: Setting prohibited

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