SH7672 datasheet(329/1292 Pages) RENESAS

329 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 303 of 1262

REJ09B0437-0100

8.3.4

DMA Channel Control Registers (CHCR)

The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the

DMA transfer mode.

The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions

can be read and written to in channels 0 and 1, but they are reserved in channels 2 to 7. The TL bit

which specifies the TEND external pin function can be read and written to in channels 0 and 1, but

it is reserved in channels 2 to 7.

0000000000000000

R/W

R/(W)* R/W

R/W

0000000000000000

R/W

R/W R/(W)* R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

Note:

Only 0 can be written to clear the flag after 1 is read.



RLD





HIE

DM[1:0]

SM[1:0]

RS[3:0]

TS[1:0]

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

Transfer Count Mode

Specifies whether to transmit data once or for the count

specified in DMATCR by one transfer request. This

function is valid only at a request of the peripheral

module. Note that when this bit is set to 0, the TB bit

must not be set to 1 (burst mode). When the SCIF or

IIC3 is selected for the transfer request source, this bit

(TC) must not be set to 1.

0: Transmits data once by one transfer request.

1: Transmits data for the count specified in DMATCR

by one transfer request.



Reserved

These bits are always read as 0. The write value

should always be 0.

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