SH7672 datasheet(327/1292 Pages) RENESAS

327 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 301 of 1262

REJ09B0437-0100

Channel

Abbreviation R/W

Initial Value

Address

Access

Size

Common

DMA operation register DMAOR

R/W*

H'0000

H'FFFE1200

8, 16

0 and 1

DMA extension

resource selector 0

DMARS0

R/W

H'0000

H'FFFE1300

2 and 3

DMA extension

resource selector 1

DMARS1

R/W

H'0000

H'FFFE1304

4 and 5

DMA extension

resource selector 2

DMARS2

R/W

H'0000

H'FFFE1308

6 and 7

DMA extension

resource selector 3

DMARS3

R/W

H'0000

H'FFFE130C

Notes: 1. For the HE and TE bits in CHCRn, only 0 can be written to clear the flags after 1 is

read.

2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is

read.

8.3.1

DMA Source Address Registers (SAR)

The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the

source address of a DMA transfer. During a DMA transfer, these registers indicate the next source

address. When the data of an external device with DACK is transferred in single address mode,

SAR is ignored.

To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2-

byte, 4-byte, or16-byte address boundary respectively.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:



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