SH7672 datasheet(335/1292 Pages) RENESAS

335 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 309 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

DREQ Level

DREQ Edge Select

These bits specify the sampling method of the DREQ

pin input and the sampling level.

These bits are valid only in CHCR_0 and CHCR_1.

These bits are reserved in CHCR_2 to CHCR_7; they

are always read as 0 and the write value should always

be 0.

If the transfer request source is specified as an on-chip

peripheral module or if an auto-request is specified, the

specification by these bits is ignored.

00: DREQ detected in low level

01: DREQ detected at falling edge

10: DREQ detected in high level

11: DREQ detected at rising edge

R/W

Transfer Bus Mode

Specifies the bus mode when DMA transfers data.

Note that the burst mode must not be selected when

TC = 0.

0: Cycle steal mode

1: Burst mode

4, 3

TS[1:0]

R/W

Transfer Size

These bits specify the size of data to be transferred.

Select the size of data to be transferred when the

source or destination is an on-chip peripheral module

00: Byte unit

01: Word unit (two bytes)

10: Longword unit (four bytes)

11: 16-byte (four longword) unit

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