SH7672 datasheet(417/1292 Pages) RENESAS

417 / 1292 page

Section 11 Power-Down Modes

Rev. 1.00 Nov. 14, 2007 Page 391 of 1262

REJ09B0437-0100

(2) Canceling Software Standby Mode

Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (power-on reset). The

CKIO pin starts outputting the clock in clock mode 0, 1, or 3.

• Canceling with an interrupt

When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit

(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling

edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits

(IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC))

is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation

settling counter (WDT) used to count the oscillation settling time.

After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer

control/status register (WTCSR) of the WDT before the transition to software standby mode,

the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the

clock pulse will be supplied to the entire chip after this overflow. Software standby mode is

thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in the

case of IRQ) starts. However, if the priority level of IRQ interrupt is lower than the interrupt

mask level set in the status register (SR) of the CPU, the interrupt request is not accepted and

thus the software standby mode is not released.

When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the

CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation

settling time.

The clock output phase of the CKIO pin may be unstable immediately after detecting an

interrupt and until software standby mode is canceled. When software standby mode is

canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters

software standby mode (when the clock pulse stops) and should be low when the CPU returns

from software standby mode (when the clock is initiated after the oscillation settling). When

software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be

low when the CPU enters software standby mode (when the clock pulse stops) and should be

high when the CPU returns from software standby mode (when the clock is initiated after the

oscillation settling) (This is the same with the IRQ pin.)

• Canceling with a reset

When the

RES pin is driven low, software standby mode is released and this LSI enters the

power-on reset state. And if the

RES pin is driven high after that, the power-on reset exception

handling starts.

Keep the

RES pin low until the clock oscillation settles.

SH7672 Datasheet(PDF) 417 Page - Renesas Technology Corp