SH7672 datasheet(415/1292 Pages) RENESAS

415 / 1292 page

Section 11 Power-Down Modes

Rev. 1.00 Nov. 14, 2007 Page 389 of 1262

REJ09B0437-0100

11.3

Operation

11.3.1

Sleep Mode

(1) Transition to Sleep Mode

Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the

program execution state to sleep mode. Although the CPU halts immediately after executing the

SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules

continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin in clock mode

0, 1, or 3.

(2) Canceling Sleep Mode

Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address

error, or reset (power-on reset).

• Canceling with an interrupt

When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and

interrupt exception handling is executed. When the priority level of the generated interrupt is

equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU,

or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt

request is not accepted and sleep mode is not canceled.

• Canceling with a DMA address error

When a DMA address error occurs, sleep mode is canceled and DMA address error exception

handling is executed.

• Canceling with a reset

Sleep mode is canceled by a power-on reset.

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