SH7672 datasheet(412/1292 Pages) RENESAS

412 / 1292 page

Section 11 Power-Down Modes

Rev. 1.00 Nov. 14, 2007 Page 386 of 1262

REJ09B0437-0100

11.2.6

System Control Register 2 (SYSCR2)

SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM

(high-speed). SYSCR2 is valid only in byte access.

When the RAMWE bit is set to 1, writing to the on-chip RAM (high-speed) is enabled. When an

RAMWE bit is cleared to 0, the corresponding on-chip RAM (high-speed) area cannot be written

to. In this case, writing to the on-chip RAM (high-speed) is ignored. The initial value of an

RAMWE bit is 1.

Note that when clearing the RAMWE bit to 0 to disable the on-chip RAM, be sure to execute an

instruction to read from or write to the same arbitrary address in each page before setting the

RAMWE bit. If such an instruction is not executed, the data last written may not be written to the

on-chip RAM (high-speed). Furthermore, an instruction to access the on-chip RAM (high-speed)

should not be located immediately after the instruction to write to SYSCR2. If an on-chip RAM

(high-speed) access instruction is set, normal access is not guaranteed.

If this bit is set to 1 to enable writing to the on-chip RAM (high-speed), the SYSCR2 read

instruction must be placed immediately after the SYSCR2 write instruction. If the on-chip RAM

(high-speed) access instruction is placed immediately after the SYSCR2 write instruction, then

normal access will not be guaranteed.

Note:

See section 11.4, Usage Notes, when writing data to this register.

7654321

11111111

RRRR

R/W

Bit:

Initial value:

R/W:



RAM

WE3

RAM

WE2

RAM

WE1

RAM

WE0

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4



All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

RAMWE3

R/W

RAM Write Enable 3 (corresponding RAM addresses:

Page 3 in on-chip RAM (high-speed)*)

0: On-chip RAM (high-speed) write disabled

1: On-chip RAM (high-speed) write enabled

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