SH7672 datasheet(416/1292 Pages) RENESAS

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Section 11 Power-Down Modes

Rev. 1.00 Nov. 14, 2007 Page 390 of 1262

REJ09B0437-0100

11.3.2

Software Standby Mode

(1) Transition to Software Standby Mode

The LSI switches from a program execution state to software standby mode by executing the

SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the

CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin

also halts in clock mode 0, 1, or 3.

The contents of the CPU remain unchanged. Some registers of on-chip peripheral modules are,

however, initialized. Regarding the states of on-chip peripheral module registers in software

standby mode, see section 28.3, Register States in Each Operating Mode.

The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next

instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP

instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely

reflected in the SLEEP instruction.

The procedure for switching to software standby mode is as follows:

1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.

2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate

values to secure the specified oscillation settling time.

3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction.

SH7672 Datasheet(PDF) 416 Page - Renesas Technology Corp