SH7672 datasheet(467/1292 Pages) RENESAS

467 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 441 of 1262

REJ09B0437-0100

13.2.2

E-DMAC Transmit Request Register (EDTRR)

The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC.

When transmission of one frame is completed, the next descriptor is read. If the transmit

descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the

transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the

transmit DMAC is halted.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRR

R/W





Bit

Bit Name

Initial

value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Transmit Request

0: Transmission-halted state. Writing 0 does not stop

transmission. Termination of transmission is

controlled by the active bit in the transmit descriptor

1: Start of transmission. The relevant descriptor is

read and a frame is sent with the transmit active bit

set to 1

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