SH7672 datasheet(468/1292 Pages) RENESAS

468 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 442 of 1262

REJ09B0437-0100

13.2.3

E-DMAC Receive Request Register (EDRRR)

EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. When

the receive request bit is set, the E-DMAC reads the relevant receive descriptor. If the receive

descriptor active bit in the descriptor has the "active" setting, the E-DMAC prepares for a receive

request from the EtherC. When one receive buffer of data has been received, the E-DMAC reads

the next descriptor and prepares to receive the next frame. If the receive descriptor active bit in the

descriptor has the "inactive" setting, the RR bit is cleared and operation of the receive DMAC is

halted.

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRR

R/W





Bit

Bit Name

Initial

value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Receive Request

0: The receive function is disabled*

1: A receive descriptor is read and the E-DMAC is

ready to receive

Note:

If the receive function is disabled during frame reception, write-back is not performed

successfully to the receive descriptor. Following pointers to read a receive descriptor

become abnormal and the E-DMAC cannot operate successfully. In this case, to make

the E-DMAC reception enabled again, execute a software reset by the SWR bit in

EDMR. To make the E-DMAC reception disabled without executing a software reset,

set the RE bit in ECMR. Next, after the E_DMAC has completed the reception and

write-back to the receive descriptor has been confirmed, disable the receive function of

this register.

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