SH7672 datasheet(472/1292 Pages) RENESAS

472 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 446 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

value

R/W

Description

TABT

R/W

Transmit Abort Detection

Indicates that frame transmission by the EtherC has

been aborted because of an error during transmission.

0: Frame transmission has not been aborted or no

transmit directive

1: Frame transmit has been aborted

RABT

R/W

Receive Abort Detection

Indicates that frame reception by the EtherC has been

aborted because of an error during reception.

0: Frame reception has not been aborted or no receive

directive

1: Frame receive has been aborted

RFCOF

R/W

Receive Frame Counter Overflow

Indicates that the receive FIFO frame counter has

overflowed.

0: Receive frame counter has not overflowed

1: Receive frame counter overflows

ADE

R/W

Address Error

Indicates that the memory address that the E-DMAC

tried to transfer is found illegal.

0: Illegal memory address not detected (normal

operation)

1: Illegal memory address detected

Note: When an address error is detected, the E-DMAC

halts transmitting/receiving. To resume the

operation, set the E-DMAC again after software

reset by means of the SWR bit in EDMR.

ECI

EtherC Status Register Interrupt Source

This bit is a read-only bit. When the source of an

ECSR interrupt in the EtherC is cleared, this bit is also

cleared.

0: EtherC status interrupt source has not been

detected

1: EtherC status interrupt source has been detected

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