SH7672 datasheet(503/1292 Pages) RENESAS

503 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 477 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

value

R/W

Description

RDLE

R/W

Receive Descriptor List Last

After completion of the corresponding buffer transfer,

the E-DMAC references the first receive descriptor.

This specification is used to set a ring configuration for

the receive descriptors.

0: This is not the last receive descriptor list

1: This is the last receive descriptor list

29, 28

RFP[1:0]

R/W

Receive Frame Position

These two bits specify the relationship between the

receive buffer and receive frame.

00: Frame reception for receive buffer indicated by this

descriptor continues (frame is not concluded)

01: Receive buffer indicated by this descriptor

contains end of frame (frame is concluded)

10: Receive buffer indicated by this descriptor is start

of frame (frame is not concluded)

11: Contents of receive buffer indicated by this

descriptor are equivalent to one frame (one

frame/one buffer)

RFE

R/W

Receive Frame Error

Indicates that one or other bit of the receive frame

status indicated by bits 25 to 16 is set. Whether or not

the receive frame status information is copied into this

bit is specified by the transmit/receive status copy

enable register.

0: No error during reception

1: A certain kind of error occurred during reception

RCSE

R/W

Determination of Receive Packet Checksum Value

When CSEBL = 1 and CSMD = 1, the setting shown in

table 13.1 occurs depending on the received packet

and data.

The information in this bit will be invalid if operation is

based on any setting other than the above.

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