SH7672 datasheet(130/1292 Pages) RENESAS

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Section 4 Cache

Rev. 1.00 Nov. 14, 2007 Page 104 of 1262

REJ09B0437-0100

23 22

13 12 11

29 28

43210

111100000

111100010

*----------*

LRU

000

23 22

13 12 11 10

23 22

13 12 11 10

11 10 9

43210

23 22

13 12 11

29 28

43210

111100001

111100011

LRU

000

23 22

13 12 11 10

23 22

13 12 11 10

11 10 9

43210

1. Instruction cache

1.1 Address array access

(a) Address specification

Read access

Write access

(b) Data specification (both read and write accesses)

1.2 Data array access (both read and write accesses)

(a) Address specification

Tag address (28 to 11)

Entry address

(b) Data specification

Longword data

Don't care

Bit 10 of entry address for read, don't care for write

0 for read, don't care for write

[Legend]

Entry address

Tag address (28 to 11)

Entry address

Longword data

2.2 Data array access (both read and write accesses)

(a) Address specification

(b) Data specification

2. Operand cache

2.1 Address array access

(a) Address specification

Read access

Write access

(b) Data specification (both read and write accesses)

Figure 4.4 Specifying Address and Data for Memory-Mapped Cache Access

SH7672 Datasheet(PDF) 130 Page - Renesas Technology Corp

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