SH7672 datasheet(134/1292 Pages) RENESAS

134 / 1292 page

Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 108 of 1262

REJ09B0437-0100

Type

Exception Handling

Priority

Ethernet controller (EtherC)

2C bus interface 3 (IIC3)

Stream interface (STIF)

Serial communication interface with FIFO

(SCIF)

Serial sound interface_0 (SSI_0)

Serial sound interface_1 (SSI_1)

Interrupt

On-chip peripheral modules

SD host interface (SDHI)

Trap instruction (TRAPA instruction)

General illegal instructions (undefined code)

Instruction

Slot illegal instructions (undefined code placed directly after a delayed

branch instruction*

1 (including an FPU instruction or FPU-related CPU

instruction in FPU module standby mode), instructions that rewrite the

PC*

2, 32-bit instructions*3, RESBANK instruction, DIVS instruction, and

DIVU instruction)

High

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF.

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.

3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,

BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,

MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.

SH7672 Datasheet(PDF) 134 Page - Renesas Technology Corp