SH7672 datasheet(138/1292 Pages) RENESAS

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Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 112 of 1262

REJ09B0437-0100

Exception Sources

Vector

Numbers

Vector Table Address Offset

Integer division exception

(division by zero)

H'00000044 to H'00000047

Integer division exception (overflow)

H'00000048 to H'0000004B

(Reserved by system)

H'0000004C to H'0000004F

H'0000007C to H'0000007F

Trap instruction (user vector)

H'00000080 to H'00000083

H'000000FC to H'000000FF

External interrupts (IRQ),

on-chip peripheral module interrupts*

511

H'00000100 to H'00000103

H'000007FC to H'000007FF

Note:

The vector numbers and vector table address offsets for each external interrupt and on-

chip peripheral module interrupt are given in table 6.4 in section 6, Interrupt Controller

(INTC).

Table 5.4

Calculating Exception Handling Vector Table Addresses

Exception Source

Vector Table Address Calculation

Resets

Vector table address = (vector table address offset)

= (vector number)

× 4

Address errors, register bank

errors, interrupts, instructions

Vector table address = VBR + (vector table address offset)

= VBR + (vector number)

× 4

Notes: 1. Vector table address offset: See table 5.3.

2. Vector number: See table 5.3.

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