SH7672 datasheet(139/1292 Pages) RENESAS

139 / 1292 page

Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 113 of 1262

REJ09B0437-0100

5.2

Resets

5.2.1

Input/Output Pins

Table 5.5 shows the reset-related pin configuration.

Table 5.5

Pin Configuration

Pin Name

Symbol

I/O

Function

Power-on reset

RES

Input

When this pin is driven low, this LSI shifts to the power-

on reset processing

5.2.2

Types of Reset

A reset is the highest-priority exception handling source. There are two kinds of reset, power-on

and manual. As shown in table 5.6, the CPU state is initialized in both a power-on reset and a

manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip

peripheral module registers are initialized by a power-on reset, but not by a manual reset.

Table 5.6

Reset States

Conditions for Transition to Reset State

Internal States

Type

RES H-UDI Command MRES

WDT

Overflow

CPU

On-Chip

Peripheral

Modules, I/O Port

WRCSR of

WDT, FRQCR of

CPG

Low

—

Initialized

High

H-UDI reset assert

command is set

—

Initialized

Power-on

reset

High

Command other

than H-UDI reset

assert is set

—

Power-on

reset

Initialized

Not initialized

High

Command other

than H-UDI reset

assert is set

Low

—

Initialized

Not initialized*

Not initialized

Manual

reset

High

Command other

than H-UDI reset

assert is set

High

Manual

reset

Initialized

Not initialized*

Not initialized

Note:

The BN bit in IBNR of the INTC is initialized.

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