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SH7672 Datasheet(PDF) 135 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 135 Page - Renesas Technology Corp |
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135 / 1292 page ![]() Section 5 Exception Handling Rev. 1.00 Nov. 14, 2007 Page 109 of 1262 REJ09B0437-0100 5.1.2 Exception Handling Operations The exception handling sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Timing of Source Detection and Start of Handling Power-on reset Starts when the RES pin changes from low to high, when the H-UDI reset negate command is set after the H-UDI reset assert command has been set, or when the WDT overflows. Reset Manual reset Starts when the WDT overflows. Address error Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Interrupts Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Bank underflow Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. Register bank error Bank overflow In the state where saving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. Trap instruction Starts from the execution of a TRAPA instruction. General illegal instructions Starts from the decoding of an undefined code (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode) anytime except immediately after a delayed branch instruction (delay slot). Slot illegal instructions Starts from the decoding of an undefined code placed (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode) immediately after a delayed branch instruction (delay slot), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Instructions Integer division instructions Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value (H'80000000) by −1. |
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