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SH7672 Datasheet(PDF) 217 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 217 Page - Renesas Technology Corp |
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217 / 1292 page  Section 7 Bus State Controller (BSC) Rev. 1.00 Nov. 14, 2007 Page 191 of 1262 REJ09B0437-0100 Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles |
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