SH7672 datasheet(220/1292 Pages) RENESAS

220 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 194 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

5 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

HW[1:0]

R/W

Delay Cycles from RD,

WEn Negation to Address,

CS5 Negation

Specify the number of delay cycles from RD and

WEn

negation to address and

CS5 negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

• CS6WCR

0000000000000000

RRRRRRRRRRR

R/W

RRRR

0000010100000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

-----------

BAS

----

SW[1:0]

WR[3:0]

HW[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

BAS

R/W

SRAM with Byte Selection Byte Access Select

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read/write access

cycle and asserts the RD/

WR signal at the write

timing.

SH7672 Datasheet(PDF) 220 Page - Renesas Technology Corp

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