SH7672 datasheet(219/1292 Pages) RENESAS

219 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 193 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

15 to 13



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

12, 11

SW[1:0]

R/W

Number of Delay Cycles from Address,

CS5 Assertion

RD, WEn Assertion

Specify the number of delay cycles from address and

CS5 assertion to RD and WEn assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

10 to 7

WR[3:0]

1010

R/W

Number of Read Access Wait Cycles

Specify the number of cycles that are necessary for

read access.

0000: No cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

R/W

External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait input is valid

1: External wait input is ignored

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